1. Field of the Invention
The present invention relates to a semiconductor device wafer and, more particularly, to the wafer regions constituting scribe lines.
2. Description of the Prior Art
In the art of fabricating semiconductor devices, when the interlayer insulation films formed between wiring regions on a semiconductor substrate by CVD are subjected to a predetermined processing involving a fine processing technique, all the interlayer films on the scribe lines are removed. Similarly, when wiring films formed by sputtering are processed, all the wiring films on the scribe lines are removed. As a result, when the structure of the device has been completed, the semiconductor substrate is generally exposed along the scribe lines to remove all the films which were sequentially formed in the process of fabricating the semiconductor device.
For example, FIG. 2 is a schematic sectional view of the structure of a chip and a scribe line in a conventional MOS-type semiconductor device having one layer of gate wiring and two layers of metal wiring.
In FIG. 2, the reference numeral 1 represents a semiconductor substrate, 2 a scribe line, 3 a part of a chip and 4 a LOCOS film constituting a device isolation region. The chip 3, namely a semiconductor device, is composed of a source and a drain 5 formed in the semiconductor substrate 1, a gate insulating film 6 formed on the semiconductor substrate 1 and a gate electrode layer 7 formed thereon. As is clear from FIG. 2, the scribe line area is in the form of a deep groove with the surface of the semiconductor substrate 1 exposed along the scribe line 2 and with the gate electrode layer 7, interlayer insulation films 8, 10 and metal wiring 9, 11 removed. This is because in fabricating a general semiconductor device, the surface of the semiconductor substrate 1 is constantly exposed on the scribe line while the interlayer insulation films and the metal wirings are formed on the semiconductor substrate 1 in the chip area. The difference in height between the surface of the semiconductor chip 3 and the surface of the scribe line 2 increases as the fabricating steps proceed. The interlayer insulation film 8 is formed between the gate electrode wiring 7 and the first metal wiring 9, and interlayer insulation film 10 is formed between the first metal wiring 9 and the second metal wiring 11.
The reference numeral 17 identifies one of the contact holes for bringing the source and drain 5 and the first metal wiring 9 into contact with each other. The reference 18 is a contact hole for bringing the first metal wiring 9 and the second metal wiring 11 into contact with each other. The reference numeral 19 denotes a bonding pad.
As described above, in order to prevent various mechanical strains, due to machining for scribing, or dicing, the semiconductor device to produce chips, from exerting a deleterious influence in the chips, the semiconductor substrate 1 is exposed on the scribe line 2 such that the scribe line area is formed as a deep groove.
A drawback of the above-described conventional semiconductor device, however, is that formation of the scribe line requires a complicated process. That is, the steps of removing the film which was laminated on the scribe line simultaneously with the formation of the wiring film, the interlayer insulation film, a passivation film, and the like are required every time each film is formed on the semiconductor substrate in the chip areas.
The concrete problem in the manufacturing process will be explained in the following with reference to the accompanying drawings.
FIG. 3 is a sectional view of a semiconductor device during a fine processing step. After a metal wiring film 14 is formed on the interlayer insulation film 10 by sputtering, a resist film 13 is applied to the metal wiring film 14 so as to form the metal wiring 11. As is obvious from FIG. 3, the thickness of the resist film 13 on the chip 3 is different from the thickness of the resist film 13 on the scribe line 2; the resist film on the scribe line 2 is relatively thick. This is because when a resist is applied to an uneven surface of a semiconductor wafer by spin coating, the resist film generally becomes thin at protruding portions and thick at recessed portions in comparison with the case of applying a resist to a flat wafer surface. In the structure of a conventional semiconductor device in which all the films on the scribe line 2 are removed, since the groove along the scribe line 2 is deeper than recessed portions in the chip 3, the,thickness of the resist film becomes especially large on the scribe line 2.
For the purpose of patterning the resist film, the resist film is appropriately exposed by an exposing apparatus so as to form a predetermined resist pattern. It is generally known that the exposure necessary for obtaining a predetermined resist pattern increases with the thickness of the resist film. There are two kinds of resists, namely, a positive type resist and a negative type resist. A positive type resist is generally used for fine processing. The following explanation relates to a positive type resist. Since the thickness of the resist film becomes especially large on the scribe line 2, an exposure appropriate for the chip 3 is insufficient for the scribe line 2, thereby leaving some part of the resist film unexposed.
FIG. 4 is a sectional view of the semiconductor device shown in FIG. 3 after resist film 13 is patterned. As is clear from FIG. 4, unexposed resist film areas 15 remain on the side walls of the groove on the scribe line 2. The metal wiring 11 is next formed while using the resist pattern 13 as a mask. The unexposed resist film 15 also works as a mask, and a narrow partial metal wiring film 16 remains on the side wall of the groove on the scribe line 2, as shown in FIG. 5, after the unexposed resist film is removed. The narrow partial metal wiring film 16 easily slips off during an after-treatment step such as the step of removing the resist pattern after the etching of the metal wiring film 14, and parts of the separated metal wiring film 16 can then adhere onto the surface of a chip 3, thereby disadvantageously lowering chip yield and quality. This occurs because the narrow partial metal wiring film 16 tends to behave like fine dust.
Various marks necessary at the time of fabrication, such as an alignment mark for an exposing apparatus, are generally placed on the scribe line. FIG. 6 is a sectional view of a semiconductor device in the state after the steps for forming an alignment mark 20 for an exposing apparatus from the metal wiring film 11 and removing a passivation film from the bonding pad 19. As is obvious from FIG. 6, an undercut etching is performed on the interlayer insulation film 10 right under alignment mark 20. This is produced because the scribe line area 2 is simultaneously etched when the passivation film 12 is etched. The alignment mark 20 with the undercut etching produced in this way easily slips off of film 10, during etching or in an after-treatment step after etching, thereby producing a problem similar to that above with reference to film 16 in FIG. 5.